1. Field of the Invention
The present invention relates to a method for fabricating a transistor, more particularly to a method for fabricating a transistor including a field effect transistor, while enabling the threshold voltage control.
2. Description of the Related Art
In general, a MOS (Metal Oxide Semiconductor) transistor in a field effect transistor includes a source region 11 and a drain region 12 on a semiconductor substrate 10, as shown in a cross-sectional view of FIG. 1. In the MOS transistor, a gate electrode 13 is formed on a gate oxide film (gate insulator) 14 provided between these regions 11 and 12.
The characteristic of a threshold voltage Vth (a voltage when the transistor is turned on) of a transistor is significantly affected by the thickness of a gate oxide film and the size of a gate. However, the threshold voltage Vth of a transistor sometimes cannot attain its target value depending on how well these constituents are formed. A method for correcting the transistor characteristic after fabricating the gate of the transistor, corresponding to how well the gate is formed, is disclosed in Publication of Unexamined Patent No. 2000-114276 (conventional example 1) or in Publication of Unexamined Patent No. 2001-176986 (conventional example 2).
In the conventional example 1, when the source region 11 and drain region 12 and the gate electrode 13 on the gate oxide film (insulator) 14 are formed on the semiconductor substrate 10, ion implantation for correction 20a is performed from an oblique direction, as shown in the cross-sectional view of FIG. 2.
The conventional example 1 is one correcting the transistor characteristic in such a manner that the ions are introduced into even a lower part of the gate electrode 13 by performing the correction ion implantation 20a from the oblique direction.
Moreover, in the conventional example 2, as shown in a flowchart of FIG. 3, impurity implantation for controlling a threshold value and annealing for activating source and drain regions are performed in areas just below gates of CMOS transistors formed on a plurality of wafers (Step S1). Thereafter, boron is implanted so that a region at a predetermined depth from the wafer surface has an impurity concentration at its peak, and phosphorus of an approximately equal amount to boron is implanted into the same region so as to have the impurity concentration at its peak therein (Step S2). Then, a threshold voltage of the wafer is measured (Step S3), and based on the measurement result (Step S4), annealing is performed for the wafer which requires the threshold voltage adjustment to activate boron and phosphorus (Step S6).
In this case, in the region at the predetermined depth from the wafer surface, variation in the impurity concentration is suppressed to maintain reliability to hot electrons. At the same time, on the wafer surface, the threshold value is arbitrarily adjusted by the variation of the impurity concentration due to the annealing.
However, in the case of the conventional example 1, when the ion implantation for correction 20a is performed from the oblique direction, the number of process steps is increased. Moreover, a drawback such as lowered reliability of the element or the like has arisen due to the damage caused by the ion implantation performed even to the sidewall of the gate oxide film.
Moreover, in the case of the conventional example 2, the annealing is performed for the wafer that requires the threshold voltage adjustment to activate boron and phosphorus. However, the threshold voltage could not be adjusted to a predetermined specific value.